module OH_SOH_LOOP_OHRAM_WRAP(
    CLKA,
    WEA,
    ADDRA,
    DINA,
    CLKB,
    ADDRB,
    DOUTB
   );

input                    CLKA;
input                    WEA;
input[9:0]               ADDRA;
input[17:0]              DINA;
input                    CLKB;
input[9:0]               ADDRB;
output[17:0]             DOUTB;



XLNX_V6LX_B18K_SDP_18_18           INST_RAM(
   .clka                           ( CLKA ),
   .wea                            ( WEA ),
   .addra                          ( ADDRA[9:0] ),
   .dina                           ( DINA[17:0] ),
   .clkb                           ( CLKB ),
   .addrb                          ( ADDRB[9:0] ),
   .doutb                          ( DOUTB[17:0] )
);

endmodule
